Semiconductor devices have dramatically decreased in size in the last few decades. Modern devices include features that are 350 nanometers, 90 nanometers, and 65 nanometers in size and often even smaller.
As device and feature sizes continue to shrink, the metallized lines and vias interconnecting the devices must both shrink and become more densely packed. Consequently, the resistance R of the interconnects and the parasitic capacitance C between neighboring interconnects both increase, increasing interconnect RC delay until it becomes a serious limiting factor in processing speed.
Using copper as the interconnect metal, surrounding the copper with low-dielectric-constant (“low-k”) material, or both can reduce the interconnect-related delay. Obstacles to implementation include the tendency of copper to diffuse through dielectrics, form deep energy levels in silicon, and react with silicon to form silicides. All of these can cause device deterioration and failure.
To block copper diffusion, various barrier layers and multi-layer barrier stacks are placed between the copper and nearby materials. Desirable characteristics of a copper-barrier layer include low resistivity, low reactivity with copper, good adhesion to copper and surrounding materials and, where high-aspect ratio features must be conformally coated, good step and bottom coverage to provide uniform thickness over side-walls and bottoms of trenches as well as on plateaus. The processing parameters (e.g. temperature and precursor composition) must also be compatible with other required processes and not harmful to other materials and structures on the substrate.
Refractory metals and their associated nitrides are popular copper-barrier materials. In some fabrication processes, it is desirable to etch both the copper and the barrier layer in a single processing step, but to etch them at selectably different rates. Chemically basic etch solutions such as APM (ammonia/hydrogen peroxide mixtures) and TMAH (Tetramethylammonium hydroxide) efficiently etch metals such as copper without unacceptably damaging hard-mask materials such as SiO2. However, they are very slow to etch liner and barrier materials such as tantalum nitride. Acid cleans, by contrast, etch both conductive metals and barrier layers quickly but also etch the hard-mask materials quickly. Therefore, a need exists for a range of etchant formulations to selectively etch copper and barrier materials without unacceptable damage to SiO2 hard-masks and other nearby dielectrics.